This relates generally to integrated circuits and more particularly, to integrated circuit packages with more than one integrated circuit die.
As demands on integrated circuit technology continue to outstrip even the gains afforded by ever decreasing device dimensions, an increasing number of applications demand a packaged solution with more integration than is possible in one silicon die. In an effort to meet this need, more than one IC die may be placed within an integrated circuit package (i.e., a multichip package). As different types of devices cater to different types of applications, more IC dies may be required in some systems to meet the requirements of high performance applications. Accordingly, to obtain better performance and higher density, a multichip package may include multiple dies arranged laterally along the same plane or may include multiple dies stacked on top of one another.
In such multichip package solutions, a multichip package will typically include a main logic die, transceiver dies, and high bandwidth memory (HBM) dies all mounted on a common interposer substrate within the multichip package. In such scenarios, the main logic die has to include transceiver input/output (IC) components for interfacing with the transceiver dies and HBM input/output components for interfacing with the high bandwidth memory dies.
The HBM interface uses a differential clock signal to latch row and column command/address signals while using a data strobe signal to latch the write data signals for the HBM memory dies. The write data strobe signals that accompany the transmitted write data signals generally do not have vastly different toggling behavior compared to the write data signals. In contrast, the differential clock signal toggles almost indefinitely while the row and column command/address signals toggle much less frequently in comparison to the clock signal.
The high activity factor of the clock signal degrades the n-channel metal-oxide-semiconductor (NMOS) transistors in the clock driver due to the hot carrier injection (HCI) phenomenon. On the other hand, the low activity factor of the command/address signals with the p-channel metal-oxide-semiconductor (PMOS) transistors in the command/address signal drivers driving those signals high will cause the PMOS transistors in the drivers to degrade due to the negative bias temperature instability (NBTI) phenomenon. When the clock signal is driven by weakened NMOS transistors and when the row and column command/address signals are driven by weakened PMOS transistors, the resulting timing margin is substantially reduced.
It is within this context that the embodiments described herein arise.